FLAT-WRAP™

Viasystem’s Engineering Teams has developed an innovative process: FLAT-WRAP™ Technology.

This patented technology eliminates the need for additional surface plated copper required to meet the IPC specification for wrap plating (ref. IPC 6012B Amendment 1 p. 3.6.2.11.1). FLAT-WRAP™ Technology results in consistent wrap plate thickness matching the thickness of the initial surface foil.

FLAT-WRAP™ Technology is suited for design applications with multiple wrap plating requirements and fine pitch trace and space on plated layers, typically sequential lam jobs or standard thru hole Via-In-Pad requiring conductive or non-conductive via fill.

Conventional processing methods to satisfy the wrap plating requirements limit the fabricator’s capability for producing high-density surface features. Fine pitch trace and space limitations are magnified in designs requiring multiple wrap plating or sequential lamination steps. Efforts to maintain minimum wrap plating thicknesses in PCBs manufactured with conventional wrap plating often lead to design compromises and/or deviations.

Viasystems FLAT-WRAP™ Technology provides the following benefits:

• Increased reliability due to wrap plate uniformity over the entire panel surface
• Elimination of copper thickness build-up during multiple wrap plating cycles on a common layer
• Improved surface plating distribution provides consistent impedance values on the plated layers with via-filled holes
• Improved dielectric thickness on all sub-laminations between the sub-outer plated layer and the subsequent laminated layer
• Reduced surface copper thickness enables designs with fine lines and tighter geometries
• Improved soldermask thickness uniformity due to reduced copper feature height

• FLAT-WRAP™ On

  Viasystems FLAT-WRAP™ Technology (3x wrap on a common layer after 6x thermal stress)

• FLAT-WRAP™ Off

  Conventional Wrap Plating (3x wrap on a common layer after 6x thermal stress)